ECE 156A - Digital Design With VHDL and Synthesis

Institution:

University of California-Santa Barbara

Subject:

Electrical Computer Engineering

Description:

Introduction to VHDL basic elements. VHDL simulation concepts. VHDL concurrent statements with examples and applications. VHDL subprograms, packages, libraries and design units. Writing vhdl for synthesis. Writing VHDL for finite state machines. Design case study.

Credits:

4.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.ucsb.edu

Phone Number:

(805) 893-8000

Regional Accreditation:

Western Association of Schools and Colleges

Calendar System:

Quarter

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