EEE 234 - Digital Integrated Circuit Design

Institution:

California State University-Sacramento

Subject:

Description:

The background and techniques needed to design and layout digital circuits at the transistor level for mixed-signal integrated circuits are covered. Topics include the design, layout and characterization of digital logic gates at the transistor level, typical CMOS process flows, device models and physics, and chip level considerations. Prerequisite: EEE 230 or instructor permission. Graded: Graded Student. Units: 3.0

Credits:

3.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.csus.edu

Phone Number:

(916) 278-6011

Regional Accreditation:

Western Association of Schools and Colleges

Calendar System:

Semester

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