CPE 273 - Hierarchical Digital Design Methodology

Institution:

California State University-Sacramento

Subject:

Description:

Advanced logic modeling, simulation, and synthesis techniques. Topics include modeling, simulation, and synthesis techniques, using Hardware Description Language (HDL's), Register Transfer Level (RTL) representation, high level functional partitioning, functional verification and testing, computer-aided logic synthesis, logical verification and testing, timing and delay analysis, automated place and route process', and design with Application Specific Integrated Circuits (ASICs) and programmable logic. Prerequisite: CSC 205, EEE 285 or their equivalents. Graded: Graded Student. Units: 3.0

Credits:

3.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.csus.edu

Phone Number:

(916) 278-6011

Regional Accreditation:

Western Association of Schools and Colleges

Calendar System:

Semester

The Course Profile information is provided and updated by third parties including the respective institutions. While the institutions are able to update their information at any time, the information is not independently validated, and no party associated with this website can accept responsibility for its accuracy.