CSC 242 - Computer-Aided Systems Design and Verification

Institution:

California State University-Sacramento

Subject:

Description:

Design and verification methodology using hardware description and verification languages (HDVLs). Advances in IC chip design; introduction to HDVLs such as System Verilog; HDVL language basics including data types, arrays, structures, unions, procedural blocks, tasks, functions, and interface concepts; design hierarchy; verification planning and productivity; verification infrastructure; guidelines for efficient verification of large designs; assertion-based verification; comprehensive computer-related design projects. Prerequisite: CSC 205 or CSC/EEE 273. Graded: Graded Student. Units: 3.0

Credits:

3.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.csus.edu

Phone Number:

(916) 278-6011

Regional Accreditation:

Western Association of Schools and Colleges

Calendar System:

Semester

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