CSE 372 - Computer Organization and Design Lab

Institution:

University of Pennsylvania

Subject:

Description:

Corequisite(s): CSE 371. Laboratory for CSE 371. In this laboratory section, students gain experience with digital design techniques by designing and implementing actual circuits using Verilog HDL and FPGAs. Five assignments culminate in the design and simulation of a complete 16-bit integer pipelined CPU.

Credits:

3.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.upenn.edu

Phone Number:

(215) 898-5000

Regional Accreditation:

Middle States Association of Colleges and Schools

Calendar System:

Semester

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