CST 441 - Logic Synthesis with VHDL

Institution:

Oregon Institute of Technology

Subject:

Description:

(2-3-3) This course will show students how to use the hardware description language, VHDL, with hierarchical design techniques to manage a complex design. In this process, students will create a design using the VHDL modeling tools, simulate the design using advanced simulation techniques, synthesize and test the design. Laboratory integral with the course. Prerequisite: CST 351 or instructor consent.

Credits:

3.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Multiple

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.oit.edu

Phone Number:

(541) 885-1000

Regional Accreditation:

Northwest Commission on Colleges and Universities

Calendar System:

Quarter

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