ECE 410 - Integrated Circuit Physical Design

Institution:

Boise State University

Subject:

Description:

CMOS IC layout, modeling, parasitic capacitance extraction, SPICE simulation. Design of static and dynamic logic gates, counters, registers, memories. Students will produce a verified layout file that can be used to build a set of photomasks for fabrication in either a foundry or in ECE 440. PREREQ: ECE 322.

Credits:

3.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.boisestate.edu

Phone Number:

(208) 426-1011

Regional Accreditation:

Northwest Commission on Colleges and Universities

Calendar System:

Semester

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