CEG 459 - Integrated Circuit Design Synthesis with VHDL

Institution:

Wright State University-Main Campus

Subject:

Computer Engineering

Description:

(Also listed as EE 459.) Application of VHSIC hardware description language (VHDL) to the design, analysis, multi level simulation, and synthesis of digital integrated circuits. A commercial set of CAD tools (Mentor Graphics) will be used in the laboratory portion of the course. Credit Hours: 4.000 Lecture hours: 4.000 Levels: Undergraduate Schedule Types: Lecture Restrictions: Must be enrolled in one of the following Colleges: College of Egr & Computer Sci Corequisites: CEG 459L Prerequisites: CS 220 and CEG 260

Credits:

4.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.wright.edu

Phone Number:

(937) 775-3333

Regional Accreditation:

North Central Association of Colleges and Schools

Calendar System:

Semester

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