CPE 166 - Advanced Logic Design

Institution:

California State University-Sacramento

Subject:

Description:

VHDL and Verilog Hardware Description Languages are studied and used on the following advanced level logic design topics: synchronous state machines, asynchronous state machines, metastability, hazards, races, testability, boundary scan, scan chains, and built-in self-tests. Commercial Electronic Design Automation (EDA) toolsets are used to synthesize lab projects containing a hierarchy of modules into Field Programmable Gate Arrays (FPGAs). Post synthesis simulations by these same tools verify the design before implementation on rapid prototyping boards in the lab. Prerequisite: CPE 64, ENGR 17. Graded: Graded Student. Units: 4.0

Credits:

4.00

Credit Hours:

Prerequisites:

Corequisites:

Exclusions:

Level:

Instructional Type:

Lecture

Notes:

Additional Information:

Historical Version(s):

Institution Website:

www.csus.edu

Phone Number:

(916) 278-6011

Regional Accreditation:

Western Association of Schools and Colleges

Calendar System:

Semester

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